UP ONE LEVEL:
ENCM 369 Winter 2004 Course Handouts
ENCM 369: Computer Organization
Lab 8 - for the week of March 22, 2004
Author: Steve Norman
Paper copies handed out: Monday, March 22, 2004
Last modified: Wed Mar 24 13:14:49 MST 2004
Contents
Updates / Corrections
- Early afternoon, Wed Mar 24:
In Exercise B the loop
you were given executes only once, not twice, with the given
data.
A correction has been made.
No programming this week!
This week you will not be doing any programming in ENCM 369.
All of this week's exercises are oriented towards understanding
the processor designs presented in Chapter 5 of your textbook.
Your understanding of these processor designs will be tested
on the final exam.
So please take this lab seriously despite the lack of programming exercises.
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You may work in pairs on this assignment
You may complete this assignment individually or with one partner,
who must be in the same lab section as you.
Two students working together should hand in a single
assignment with both names on the cover page.
Students working in pairs must make sure both partners understand
all of the exercises being handed in.
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Due Dates
The Due Date for this assignment is 1:30pm, Monday, Mar. 29.
The Late Due Date is 1:30pm, Tuesday, Mar. 30.
The penalty for handing in an assignment after the Due Date but
before the Late Due Date is 3 marks.
In other words,
X/Y becomes (X-3)/Y if the assignment is late.
There will be no credit for assignments turned in after
the Late Due Date;
they will be returned unmarked.
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Marking scheme
A: 6 marks /
B: 5 marks /
C: 3 marks /
D: 3 marks /
E: 3 marks /
F: 3 marks
total: 23 marks
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Exercise A: Supporting more instructions
Read This First
A good way to see whether you understand the design of the circuit
of Figure 5.19 is to try to enhance it to support
more instructions.
What to do
- Do Exercise 5.5 on page 427 of Patterson and Hennessy.
In addition to showing any needed datapath modifications
and additional control signals, make it clear what the values
of all the control signals should be.
- Do Exercise 5.7 on page 427 of Patterson and Hennessy.
In addition to showing any needed datapath modifications
and additional control signals, make it clear what the values
of all the control signals should be.
- Think about adding support for the ori
and andi instructions.
Write a few paragraphs to describe in detail the kinds of changes
you would have to make to the organization of the
circuit, but do not get down to the level
of specifying what all the control signal values would have
to be for the two instructions.
(I realize that this is a somewhat vague description of
what is desired, but if I were really precise about
what I wanted I would be giving away too many hints about
the answer.)
Hand in your answers to questions 1, 2, and 3.
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Exercise B: Instruction execution in the multicycle datapath
Read This First
This problem is to help you make sure you understand the roles
of the ALU and some of the control signals in
Figure 5.33 in Patterson and Hennessy.
What to do
Original WRONG information, which you should NOT USE:
Consider the following sequence of instructions:
loop:
lw $t5, 0($s3)
sub $s3, $s3, $t1
beq $t5, $zero, loop
Suppose the address of the lw instruction
is 0x004001f8
and suppose the following is true just before the lw
instruction is executed the first time:
- The value in $s3 is 0x10010304.
- The value in $t1 is 4.
- The value of the word at address 0x10010304
is 0x00123400.
- The value of the word at address 0x10010300 is 0.
It will take 24 clock cycles for the machine of Figure 5.33
to execute the sequence of instructions twice.
New, CORRECTED information, which you SHOULD USE:
Consider the following sequence of instructions:
loop:
lw $t5, 0($s3)
sub $s3, $s3, $t1
beq $t5, $zero, loop
Suppose the address of the lw instruction
is 0x004001f8
and suppose the following is true just before the lw
instruction is executed the first time:
- The value in $s3 is 0x10010304.
- The value in $t1 is 4.
- The value of the word at address 0x10010304
is 0.
- The value of the word at address 0x10010300 is
is 0x00123400.
It will take 24 clock cycles for the machine of Figure 5.33
to execute the sequence of instructions twice.
(The correction just swaps the contents of the two data memory words.)
For each of those 24 clock cycles, what are
- the 32-bit ALU inputs (expressed as base sixteen numbers);
- the 32-bit ALU output (expressed as a base sixteen number);
- the Zero output of the ALU (expressed as 0 or 1);
- the values of the control signals
ALUSrcA, ALUSrcB, ALUOp, PCSource,
PCWrite and PCWriteCond (expressed in base two)?
Express your answer in a legible, sensibly organized pair of tables--one
for the first 12 cycles and another for the last 12 clock cycles.
Use `don't know' to indicate that there is no way of
knowing what a particular ALU input or output is
in a particular clock cycle.
Use `X' to indicate that a control signal
is a `don't care' in a particular clock cycle.
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Exercise C: Supporting addi in the multicycle implementation
What to do
Do problem 5.15 on page 429 of Patterson and Hennessy.
Note that part of the answer will be listing all of the control
signal values for any new states added to the finite state machine.
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Exercise D: Supporting jal in the multicycle implementation
What to do
Do problem 5.17 on page 429 of Patterson and Hennessy.
Note that part of the answer will be listing all of the control
signal values for any new states added to the finite state machine.
Hint:
One thing you must do is
modify the multiplexor that controls
the 5-bit `Write register' input to the Register File.
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Exercise E: Supporting jr in the multicycle implementation
What to do
Do problem 5.22 on page 430 of Patterson and Hennessy.
In the real MIPS instruction set the op-code (bits 31-26
of the instruction) for jr is 000000, same as
for R-type instructions.
You should pretend for the sake of this exercise that
the op-code for jr is different from the
op-code for all the other instructions in the MIPS subset
supported by the machine of Figure 5.33.
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Exercise F: Exception handling
Read This First
This exercise is about the processor design of Figures 5.48 and 5.50
in Patterson and Hennessy.
If you have a recent printing of the text, your version of Fig. 5.48
should be correct. If you have an older printing, you may need to
make the following correction:
The input to the EPC register should be the 32-bit output from
the ALU, not the 32-bit output from the ALUOut register.
One other note about Figure 5.48: It does not show a one-bit signal
called Overflow, which is output from the ALU and is input
to the main control unit.
You should assume that this signal exists, and has a value of 1
if and only if there is overflow during addition or subtraction in the ALU.
What to do
Suppose the bit pattern for the
instruction at address 0x0040_0104 is (in base two)
000000_01010_01011_00101_00000_100000
(This is an add instruction.)
Assume that $t2 contains
0x4000_0000 and $t3 contains
0x5000_0000 just before the processor
fetches the above instruction.
Trace the attempted execution of this instruction.
For each of the clock cycles the processor spends in trying to
execute the instruction, determine the values
of the two ALU inputs, the ALU output,
the 32-bit PC input, the ALUOp control signal,
the PCWrite control signal, and the EPCWrite control signal.
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