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List of ENCM 369 Winter 2010 Lab Assignment Instructions (and Corrections to Instructions)

This page is maintained by Steve Norman
Last modified: Wed Apr 7 08:47:05 MDT 2010

Lab instructions will all be in PDF format. Unlike in previous years' versions of ENCM 369, your instructors will not be distributing paper copies of lab instructions.

If any corrections or clarifications are needed for a week's lab instructions, these will be listed just below the link to the lab instructions.

• Lab 1, for the week of Jan. 18


• Lab 2, for the week of Jan. 25


• Lab 3, for the week of Feb. 1

  Lab 3 correction, posted around 4:00pm Sun Jan 31: Part of the comment in the code for proc2 in Exercise D does not make sense. The sentence that starts, "From reading the code ...," should end with, "even if you didn't make a copy of delta from the $a3 register; also you might be able to think of a way to avoid copying alpha to $s0 or gamma to $s2."



• Lab 4, for the week of Feb. 8

  Minor Lab 4 corrections, posted around 10:00am Mon Feb 8 ...
  Exercise A: The adjustment to the stack pointer in the epilogue of main should be addi $sp,$sp,24. The mistake does not prevent the program from running correctly, but it may be a cause of confusion.
  Exercise C: Near the beginning of the body of main, the code for i=0 should be add $s0,$zero,$zero; the incorrect code works correctly by accident.



• Lab 5, for the week of Feb. 22


• Lab 6, for the week of Mar. 1—because of midterms, this is shorter than usual and has an extended due date.


• Lab 7, for the week of Mar. 8

  Note: The Due Date for Lab 7 has been extended until 3:30pm, Friday, March 12. Because that is later than the original Late Due Date, there will no longer be a Late Due Date.



• Lab 8, for the week of Mar. 15

  Minor correction: On page 3, there are two bullets for lwc1; the second one is actually documentation for swc1.



• Lab 9, for the week of Mar. 22

  Correction to Exercise C Part I: I forgot about the latency of the multiplexer controlled by the AND gate in Fig. 4.24. On page 4, the last three paragraphs of "What To Do Part I" should read:

  The Mux that chooses between PC+4 and the branch target has its three inputs ready at 120ps, 440ps, and 710ps. So the output of that Mux is ready 750ps after the clock edge.

  Similar work will show that the output of the Mux that feeds straight into the PC input is ready 790ps after the clock edge.

  Conclusion: For beq instructions to work correctly, given the latencies in Figure 5, the clock period for the processor must be no shorter than 790ps.



• Lab 10, for the week of Mar. 29

  Mon Mar 29 around 3:15pm: Revised corrections to Exercise A ...
  There is no and instruction—I meant to write ``add instruction.'' ``lw instruction.'' (Apologies for the confusion!) Also, I forgot to say what was in $18, which gets read into the ID/EX register even though the value doesn't get used for anything; you may either assume zero or write ``unknown'' for that value.



• Labs 11 and 12, for the weeks of Apr. 5 and 12

  Note: The last row of Table 2 for Exercise 11A does not really make sense, because if the sll instruction at 0x0040_43b4 is in the cache at all, it should be at index 237, not 238. However, this does not need to be corrected for you to do the exercise—the first access to that line 238 in the cache will be a miss that will result in putting meaningful information into that line. Sorry for the confusion.

  In Exercise 11F, sw $zero, $(a0) should read sw $zero, 0($a0).