LIST OF PUBLICATIONS:
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1. Books
2009
|
V. Shmerko, S. Yanushkevich, and S. Lyshevski, Computer
Arithmetics for Nanoelectronics, Taylor & Francis/CRC
Press,
|
2008
|
S. Yanushkevich, and V. Shmerko, Fundamentals
of Logic Design, Taylor & Francis/CRC
Press,
|
2006
|
S. Yanushkevich, D.M. Miller, V. Shmerko, and R.
Stankovic, Handbook
on Decision Diagrams, Taylor & Francis/CRC Press
|
| 2005 |
S. Yanushkevich, V. Shmerko, A. Stoica, and D. Popel, Inverse
Problems of Biometrics, CRC Press |
| 2004 |
S. Yanushkevich, V.
Shmerko, S. Lyshevski, Logic
Design of NanoICs,
CRC Press
|
| 1998 |
S. Yanushkevich,
Logic Differential Calculus in
Multi-Valued Logic
Design, Academic Publishers of Technical Univ. of Szczecin, Poland,
ISBN
83-87423-16-5, 328 p. (Habilitation thesis) HTML
FILES |
| 1991* |
Kukharev G.,
Shmerko V., Yanushkevich S.,
Technique of Binary Data
Parallel Processing on VLSI, Publishing House "High School", Minsk,
Belarus,
220p. PDF
FILE |
Edites books:
2007
|
S.
Yanushkevich, P. Wang, M. Gavrilova, S. Srihari (Editors),
Image Pattern Recognition: Synthesis and
Analysis in Biometrics, Machine Perception and Artificial
Intelligence,
Vol 67, World
Scientific Publishing Co., New Jersey-London-Singapore |
| 2004 |
S.
Yanushkevich (Editor), Artificial
Intelligence in Logic Design, Book Series: THE KLUWER INTERNATIONAL
SERIES IN ENGINEERING AND
COMPUTER SCIENCE : Volume 766, Kluwer
Academic Publishers |
Book chapters :
2009
|
S.
Yanushkevich, V. Shmerko, O. Boulanov, and A. Stoica, Decision Making
Support in Biometric-
Based Physical Access Control Systems: Design Concept, Architecture,
and Applications,
In: N. V. Boulgouris, K. N. Plataniotis, and L.
Micheli-Tzanakou (Editors), Biometrics: theory, methods, and
applications, Wiley-IEEE
Press.
|
2007
|
S.
Yanushkevich, V. Shmerko, A. Stoica, P.Wang, S. Srihari,
Introduction to Synthesis in Biometrics,
In: S.
Yanushkevich, P. Wang, M. Gavrilova, S. Srihari (Editors),
Image Pattern Recognition: Synthesis and
Analysis in Biometrics, Machine Perception and Artificial Intelligence,
Vol 67, World
Scientific Publishing Co., New Jersey-London-Singapore, pp. 5–29
|
2007
|
S.
Yanushkevich, A. Stoica, V. Shmerko, Fundamentals of Biometric-based
Training,
In: S.
Yanushkevich, P. Wang, M. Gavrilova, S. Srihari (Editors),
Image Pattern Recognition: Synthesis and
Analysis in Biometrics, Machine Perception and Artificial Intelligence,
Vol 67, World
Scientific Publishing Co., New Jersey-London-Singapore, pp. 5–29
|
2006
|
S.
Yanushkevich,
Logic Design of Nanodevices, Invited
Chapter
In: M. Rieth, W. Schommers, Editors,
Handbook of Theoretical and Computational Nanotechnology,
Scientific American Publishers, Chapter 110, pp. 1–52
|
2005
|
S.
Yanushkevich,
Computer Arithmetic, Invited Chapter
In: R. Dorf, Editor, The Electrical
Engineering Handbook, 3rd Edition, CRC Press
|
2005
|
S.
Yanushkevich, V. Shmerko, Logic Design of Nanodevices, Invited Chapter In: M. Rieth, W. Schommers, Editors, Handbook
of Theoretical and Computational Nanotechnology, Scientific American
Publishers
|
2005
|
V. Shmerko,
S. Yanushkevich, Decision
Diagram Technique, Invited Chapter In: Handbook for Electrical
Engineers,
Second Edition, CRC Press |
| 2004 |
V.
Shmerko, S. Yanushkevich, 3D Feedforward Neural
Networks and its Realization by a SET
Logic.
In book: S.
Yanushkevich (Ed.) “Artificial Intelligence in Logic Design“,
Kluwer
Academic Publishers, pp. 313-334
|
| 1990* |
Yanushkevich S.,
Systolic Arrays for Multivalued
Logic Data Processing.
In book: "Algorithms and Systolic Processors for Multivalued Data
Processing"
by Kukharev G., Shmerko V., Zaitseva E., Publishing House "Science and
Engineering", Minsk, Belarus, pp.157-252 |
PhD
thesis:
| 1992* |
Yanushkevich S., Methods to Synthesize
Parallel-Pipelining Devices
for Boolean and Multivalued Functions Transform Basing Boolean
Differential
Calculus. Thesis for the Degree of Doctor of Philosophy,
Radioengineering
Inst., Minsk, Belarus, 210p. |
|
|
2. Journal
papers
2008
|
S. Lyshevski, S. N.
Yanushkevich, V. P. Shmerko, and V. Geurkov, Computing
Paradigms for Logic
Nanocells, Journal of Computational and Theoretical Nanoscience,
American Scientific Publishers,
Volume 5, No.12, 2377–2395 |
2008
|
S. N. Yanushkevich,
V. P. Shmerko, and B. Steinbach, Spatial Interconnect Analysis for
Predictable
Nanotechnologies, Journal of Computational and Theoretical Nanoscience,
American Scientific Pub-
lishers, Volume 5, No.3, pp. 5669 |
2007
|
S. N. Yanushkevich
and V. P. Shmerko, Teaching Reed-Muller Techniques in Introductory
Classes
on Logic Design Facta Univ. Ser.: Elec. Energ., vol. 20, No. 2,
December 2007, pp. 331-365 |
2007
|
S. Yanushkevich, A.
Stoica, V. Shmerko, Synthetic Biometrics, IEEE Computational
Intelligence
Magazine, Volume 2, Number 2, May 2007, pp. 60–69 |
2007
|
S. Yanushkevich,
Spatial Systolic Array Design for Predictable Nanotechnologies, Journal
of Com-
putational and Theoretical Nanoscience, American Scientific Publishers,
Volume 4, No.3, pp.467–481 |
2007
|
S. Yanushkevich, Logic
Design of Computational Nanostructures, Journal of Computational
and
Theoretical Nanoscience, American Scientific Publishers, Volume 4,
No.3, May, pp. 384–407 |
2007
|
S. Yanushkevich, V.
Shmerko, NANO MVL STRUCTURES Guest Editorial Introduction to the
Special Issue, Int. Journal on Multiple-Valued Logic and Soft Computing
(USA), Volume 13, Number
2, 2007 |
2004
|
R.
Stankovich, S. Yanushkevich, Foreword to the Special Issure
“Arithmetical Logic in Control Systems”, “Automation
and Remote Control“ (Kluwer/Plenum Publishers), June 2004, Volume
65, Issue 6, pp. 841-841 PDF
FILE
|
| 2004 |
P.
Dziurzanskii, V. P. Shmerko, S. N. Yanushkevich, Representation
of Logical Circuits by Linear Decision Diagrams with Extension to
Nanostructures, “Automation
and Remote Control“ (Kluwer/Plenum Publishers),
June 2004, Volume 65, Issue 6, p. 920-937 PDF
FILE |
2004
|
D. V. Popel,
S. N. Yanushkevich, Modeling Combinational Circuits Using Linear
Word-level Structures, “Automation and Remote Control“ (Kluwer/Plenum Publishers),
June 2004, Volume 65,
Issue 6, pp. 1018-1032, PDF
FILE
|
| 2004 |
S.
Yanushkevich,V. Shmerko, D. Malygin, P. Dziurzanski, A. Tomaszewska,
Linearity of Word-Level
Representations of Multiple-Valued
Networks, Int. Journal on Multiple-Valued Logic (Kluwer/Plenum Publishers), Special Issue on
Spectral Technique, Vol. 10, no.2, 2004 PDF
FILE |
| 2003 |
S.
Yanushkevich, Multiplicative Properties of a Walsh Spectrum of Boolean
Function, “Automation and Remote Control“ (Kluwer/Plenum Publishers), December 2003, Volume
64, Issue 12, pp.
1938-1947 PDF
FILE |
2003
|
S.
Yanushkevich, Editorial – Artificial Intelligence in Logic Design, December 2003, Volume 20, Issue 3-4, pp.
167-168 PDF
FILE
|
| 2003 |
V.
Shmerko, S. Yanushkevich, Three-Dimensional Feedforward
Neural Networks
and Their Realization by Nano-devices, “Artificial Intelligence
Review Int. Journal“ (Kluwer
Publishers), Special Issue
on “Artificial Intelligence in Logic Design“, December
2003, Volume 20, Issue 3-4, pp. 473-494, PDF
FILE |
| 2002 |
Invited paper, P. Dziurzanski, V.
Maluygin, V. Shmerko, S. Yanushkevich,
Linear Models of Circuits Based on the Multivalued Components,
Automation
& Remote Control (Kluwer/Plenum Publishers),
vol. 63, no.6, 2002, pp. 960-980 PDF
FILE |
| 2001 |
Butler J., Dueck G., Shmerko V., Yanushkevich
S., On the Number of
Generators of Transeunt Triangles, Discrete Applied Mathematics,
no. 108, pp. 309-316 |
| 2001 |
Yanushkevich S., Matrix and Combinatorics
Solution of Boolean Differential
Equations, Discrete Applied Mathematics, 2001 PostScript
FILE |
| 2000 |
Yanushkevich S., Bochmann D., Stankovic R.,
Tosic Z., Shmerko V., Logic
Differential Calculus: Progress, Tendencies and Applications,
Automation
and Remote Control (Kluwer/Plenum
Publishers),
vol. 61, no.6, Pt. 2, pp.1033-1047
|
| 2000 |
Levashenko V., Moraga C., Shmerko V.,
Kholovinski G., Yanushkevich
S., A Test Algorithm for Multiple -Valued Combinational Circuits,
Automation
and Remote Control (Plenum/Kluwer Publishers)
, vol. 61, no. 3, Pt. 2, pp. 844-857
|
| 2000 |
Butler J. T., Dueck G. W., Shmerko V.,
Yanushkevich S. N., Comments
on Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller
Expansion
for Symmetric Functions, IEEE Transaction of Computer-Aided Design of
Integrated
Systems, vol.19, no.11, pp. 1386-1388, PostScript
FILE |
| 2000 |
Shmerko V., Popel D., Stankovic R., Cheushev V.,
Yanushkevich S, AND/EXOR
Minimization of Switching Functions Based on Information-Theoretical
Approach,
Facta Universitatis Journal, Series: Electronics and Energetics
(Yugoslavia),
vol.13, no.1, pp.11-25 PostScript
FILE |
| 1997 |
Yanushkevich S., Matrix Method to Solve Logic
Differential Equations,
IEE Proceedings, Pt.E.- Computers and Digital Technique, vol.144, no.
5,
pp.267-272 PostScript
FILE |
| 1994 |
Yanushkevich S., Systolic Synthesis Algorithms
for Arithmetic Polynomial
Forms of k-valued Functions of Boolean Algebra. Automation and Remote
Control
(Plenum/Kluwer Publishers) vol.55, no.12,
pp.1812-1823
|
| 1996 |
Levashenko V., Shmerko V., Yanushkevich S.,
Solution of Boolean Differential
Equations on Systolic Arrays, Cybernetics and System Analysis,
Ukrainian
Academy of Sciences (Translated in USA), vol.32, no.1,
pp.26-40 RUS: PDF
FILE |
| 1994 |
Yanushkevich S., Development of the Methods of
Boolean Differential
Calculus for Arithmetic Logic. Automation and Remote Control (Plenum/Kluwer
Publishers),
vol.55,
no.5, pp.715-729
|
| 1991 |
Shmerko V., Yanushkevich S., Processing of
Binary Images by Matrix
Operators of Boolean Differential Calculus and their Realization in
Linear
Systolic Arrays, Pattern Recognition & Image Analysis,
vol.1,no.4, pp.406-422 PDF
FILE |
| 1990 |
Shmerko V., Yanushkevich S., Algorithms of
Boolean Differential Calculus
for Systolic Arrays, Kibernetika, Ukrainian Academy of Sciences
(Translated
in USA), no.3 , pp.38-47 PDF
FILE |
3. Proceedings of Conferences (Refereed Papers)
2008
|
S. E. Lyshevski, V.
P. Shmerko, M. A. Lyshevski and S. N. Yanushkevich, Neuronal
processing,
reconfigurable neural networks and stochastic computing, Proc. IEEE
Conference on Nanotechnology,
Arlington, TX, 2008. |
2008
|
S. E. Lyshevski, V.
P. Shmerko and S. N. Yanushkevich, Benchmarking performance and physi-
cal limits on processing electronic device and systems: Solid-state,
molecular and natural processing
paradigms, Proc. NanoTech Conference, Boston, MA, vol. 3, pp. 31-34,
2008 |
2007
|
S. N. Yanushkevich,
A. Stoica, and V. P. Shmerko, Early Detection Support in
Biometric-Based
Physical Access Control Systems, Proc. International Conference on
Frontiers in the Convergence of
Bioscience and Information Technologies - FBIT 2007, Jeju Island,
Korea, October 2007 |
2007
|
V.P.Shmerko,
S.N.Yanushkevich, H.Moon, A.Stoica, R.R.Yager, Accelerating Decision
Making Sup-
port in Biometric Assistant for Remote Temperature Measures, ECSIS
Symposium on Bio-inspired,
Learning, and Intelligent Systems for Security - BLISS 2007, Edinburgh,
August 2007, pp. 11–14 |
2007
|
P. S. Wang, and S.
N. Yanushkevich. Biometric technologies and applications. In
Proceedings of
the 25th Conference on Proceedings of the 25th IASTED international
Multi-Conference: Artificial
intelligence and Applications (Innsbruck, Austria, February. ACTA
Press, Anaheim, CA, pp. 226-231 |
2006
|
S. N. Yanushkevich,
A. Stoica, V. P. Shmerko, Experience of Design and Prototyping of a
Multi-
Biometric Early Warning Security Systems, The Annual IEEE Conference
IECON, Paris, France,
November 2006, pp.2347–2352 |
2006
|
S. N. Yanushkevich,
A Concept of Intelligent Biometric-based Early Detection and Warning
System,
4th Annual Conference on Privacy, Security and Trust, published by
McGraw Hill/Ryerson, Markham,
ON, Canada, October 2006, pp. 429–432 |
2006
|
S. N. Yanushkevich,
A. Stoica, V. P. Shmerko, Semantic Framework for Biometric-based Access
Control System, 2006 IEEE International Conference on Computational
Intelligence for Homeland
Security and Personal Safety, pp.11–16, Alexandria, USA, October 2006. |
2006
|
S. Yanushkevich,
Synthetic Biometrics: A Survey, In: Proceedings of the World Congress
on Com-
putational Intelligence, Vancouver, July 2006 |
2006
|
S. N. Yanushkevich,
O. R. Boulanov, V. P. Shmerko, Embedding and Assembling Techniques for
Spatial Computing Structure Design using Decision Trees and Diagrams,
IEEE 36th Int. Symposium
on Multi-Valued Logic, Singapore, May 2006 |
2006
|
B. Steinbach, S. N.
Yanushkevich and V. P. Shmerko, Spatial Decomposition of Boolean
Functions
and Interconnect Analysis for Predictable Nanotechnologies,Workshop on
Boolean Problems, Freiberg,
Germany |
2005
|
Y. Luo, M. L.
Gavrilova, M. C. Sousa, J. Pivovarov, and S. Yanushkevich, Morphing
Facial Expres-
sions from Artistic Drawings, In: T. Simos, G. Maroulis, Eds., Advanced
in Computational Methods in
Sciences and Engineering. Lecture Series on Computer and Computational
Sciences, Brill Academic
Publishers, The Netherlands, Vol. 4, pp. 1507–1511 |
2004
|
S. Yanushkevich, V.
Shmerko, L. Guy, C. Lu, 3D Multiple Valued Circuits Design Based on
Single-
Electron Logic, 34th IEEE Int. Symp. on Multiple Valued Logic,
pp.275-280 |
2004
|
S. Yanushkevich, V.
Shmerko, Taylor Expansion of Logic Functions: from Conventional to
Nanoscale
Design, The 2004 Int. TICSP Workshop on Spectral Methods and Multirate
Signal Processing, Vienna,
Austria, pp.297-303 |
2004
|
Yanushkevich S., Stoica A., Srihari S., Shmerko V.,
Gavrilova M., Simulation
of Biometric Information: The New Generation of Biometric Systems.
Proc. BT2004 Int'l Workshop on Biometric Technologies, Calgary, AB,
Canada, pp.87-98
|
2004
|
Wang P., Yanushkevich S., Shmerko V., Using Polar
Transform of Orientation Map in the task of Generation of Synthetic
Fingerprints. Proc. BT2004 Int'l Workshop on Biometric
Technologies, Calgary, AB, Canada, pp.163-172 |
2004
|
S.
Yanushkevich, V. Shmerko, L. Guy, D. Lu, 3D
Multiple Valued Circuits Design Based on Single-Electron Logic, 34th
IEEE Int. Symp. on Multiple Valued
Logic, Toronto, pp. 275-280 PDF
FILE |
2003
|
S.
Yanushkevich, V. Shmerko , D. C. Lu, K. Adams, J. McGregor,
Arithmetic Spectrum Computing via Taylor
Expansion, Proc. 4th Int. Workshop on Computational Intelligence
and Information Technologies, Nis,
Yugoslavia, 2003, pp.
143 - 146 |
2003
|
Y.
Xie, S. Yanushkevich, V. Shmerko, EDNA:
Event-Driven Logic Network Analysis
Tool, Proc. 4th Int. Workshop on Computational Intelligence
and Information Technologies, Nis, Yugoslavia, 2003, pp.
125 - 128 |
2003
|
S.
Yanushkevich, Taylor-Based Technique for Walsh
Spectrum Computing, Proc. 4th Int. Workshop on Computational
Intelligence and Information Technologies, Nis, 2003, Yugoslavia,
pp. 147 - 150 |
| (2002) |
S. Yanushkevich, P. Dziurzanski, V. Shmerko,
Word-Level Models for
Efficient Computation of Multiple-Valued Functions, Part 1: LAR, 32th
IEEE
Int. Symp. on Multiple-Valued
Logic, Boston, 2002, USA, pp.202-208 PDF
FILE |
| (2002) |
S. Yanushkevich, A. Tomaszewska, V.
Shmerko, Word-Level Models
for Efficient Computation of Multiple-Valued Functions, Part 2: LWL,
32th
IEEE Int. Symp. on Multiple-Valued Logic, Boston, USA, pp. 209-
214 PDF FILE |
| (2002) |
S. Yanushkevich, et al., Linear of Word-Level
Decision Diagrams: New
Understanding, Workshop on Logic & Synthesis, New Orleans,
pp.67-72 PDF FILE |
| (2002) |
V. Cheushev, J. Kolodziejczyk, T. Luba, C.
Moraga, P. Sapiecha, V.
Shmerko, S. Yanushkevich, Information Measures to Support Logic Network
Synthesis, Systems-on-Chip for real-Time Applications (selected
publications
of the Int. Workshop on Systems-on-Chip, Banff, Canada), Kluwer, pp.
214-223 PDF FILE |
| (2002) |
M. Pleban, H. Niewiadomski, P. Buciak, P.
Sapiecha, S. Yanushkevich,
V. Shmerko, Argument Reduction Algorithm for Multi-Valued Relations,
IASTED
Conference, Banff, Canada, pp. 609-614 |
| (2001) |
Yanushkevich S., Falkowski B., Shmerko V.,
Spectral Linear Arithmetic
Approach for Multiple-Valued Functions: Overview of Applications in CAD
of Circuit Design, Proc. IEEE Int. Conf. on Information, Communication
and Signal Processing, Singapore, 2D1.6 P0586 CD |
| (2001) |
Shmerko V, Phil Phillips, Rogers W.,
Yanushkevich S., Biometrical technologies
and Personal Identification: Achievments, Tendencies and Perspectives,
Proc. Int. Conf. on Risk
Management and Insurance in Industry, Transport and Warehousing,
Yugoslavia, invited paper |
| (2001) |
Perkowski M., Jozwiak L., Kerntopf P.,
Mishchenko A., Al-Rabadi
A., Coppola A., Buller A., Song X., M. Md. Mozammel
Huq
Azad Khan, Yanushkevich S., Shmerko V.,
Chrzanowska-Jeske M., A General Decomposition for
Reversible
Logic, Proc. 5th Int. Workshop on Application of Reed-Muller Expansion
in Circuit Design, Mississippi State University, Starkville, MS,
USA , pp. 119 –138 |
| (2001) |
Dueck W., Maslov D., Butler T., Shmerko V.,
Yanushkevich S., A Method
to Find the Best Mixed Polarity Reed-Muller Expression Using Transeunt
Triangle, Proc. of the 5th Int. Reed-Muller Workshop (RM'2001),
Strkville,
Missisippi, USA, pp. 82-92 |
| (2001) |
Cheushev V., Yanushkevich S., Moraga C., Shmerko
V., Kolodzejczyk J.,
Information Theory Method for Flexible Network Synthesis, IEEE 31-th
Int.
Symposium on Multiple-Valued Logic, pp. 201-206
|
| (2000) |
Tomaszewska A., Dziurzanski P., Yanushkevich S.,
Shmerko V., Two-Phase
Exact Detection of Symmetries, IEEE 31-th Int. Symposium on
Multiple-Valued
Logic, pp. 213-216
|
| (2000) |
Bochmann D., Posthoff Ch., Shmerko V., Stankovic
R., Tosic Z., Yanushkevich
S., Logic Differential Calculus as a Part of Switching Theory, IEE 4-th
Int, Conf. on New Information Technologies in Education - NITE'2000,
Minsk,
Belarus, pp.126-135 PostScript
FILE |
| (2000) |
Dziurzanski P., Yanushkevich S., Shmerko V., On
Cost of AND-EXOR Expansion
of Switching Functions with Non-Equivalent Partial Symmetry, 6-th Int.
Conference on Advanced Computer Systems - ACS-2000, Poland, pp.
337-342 PDF FILE |
| (2000) |
Bochmann D., Posthoff Ch., Shmerko V., Stankovic
R., Tosic Z., Yanushkevich
S., State-of-the-Art of Logic Differential Calculus, Proc. Int.
Workshop
on Boolean Problems, Freiburg, Germany, pp.117-124 |
| (2000) |
Luba T., Moraga C., Yanushkevich S., Shmerko V.,
Kolodziejczyk J.,
Application of Design Style in Evolutionary Multi-Level Networks
Synthesis,
Proc. IEEE Symposium on Digital System Design (DSD'2000), Netherlands,
pp. 156-163 PostScript
FILE |
| (2000) |
Popel D., Yanushkevich S., Perkowski M.,
Dziurzanski P., Shmerko V.,
Information Theoretic Approach for Minimization of Arithmetic
Expression,
Proc. Third Oregon Symposium on Logic, Design and Learning, Portland,
Oregon,
USA (online) PostScript
FILE |
| (2000) |
Yanushkevich S., Popel D., Cheushev V., Shmerko
V., Entropy Based algorithm
for 4-Valued Functions Minimization, Proc. of the IEEE 30th Int. Symp.
on Multiple-Valued Logic, USA, pp.265-270 PostScript
FILE |
| (2000) |
T.Luba, S. Yanushkevich, M. Opoka, C. Moraga, V.
Shmerko, Evolutionary
Multi-Level Circuit Synthesis in Given Design Style, Proc. of the IEEE
30th Int. Symp. on Multiple-Valued Logic, USA, pp.253-258 PDF
FILE |
| (2000) |
Yanushkevich S., Butler J., Dueck G., Shmerko
V., Experiments on FPRM
Expressions for Partially Symmetric Logic Functions, Proc. of the IEEE
30th Int. Symp. on Multiple-Valued Logic, USA, pp.141-146 PDF
FILE |
| (1999) |
Yanushkevich S. N.,. Shmerko V. P., Dziurzanski
P., Stankovic R. S.,
Popel D. V, Experimental verification of the entropy based method for
minimization
of switching functions on pseudo ternary decision trees, IEEE Int.
Conf.
on Telecommunications in Modern Satellite, Cable and Broadcasting
Services
- TELSIKS'99 (invited paper), Yugoslavia, pp. 452-459 PDF
FILE |
| (1999) |
Shmerko V. P., Popel D. V., Stankovic R. S.,
Cheushev V. A., Yanushkevich
S. N., Information Theoretical Approach to Minimization of AND/EXOR
Expressions
of Switching Functions, invited paper, Proc. IEEE Int. Conf. on
Telecommunications
in Modern Satellite, Cable and Broadcasting Services - TELSIKS'99,
Yugoslavia,
pp. 444-451 PostScript FILE |
| (1999) |
Butler J., Dueck G., Shmerko V., Yanushkevich
S., On Recognition of
Symmetric Switching Functions in Reed-Muller Form, invited paper, Proc.
Int. Conf. on Pattern Recognition & Information Processing, Minsk,
Belarus, pp.215-234 PostScript
FILE |
| (1999) |
Levashenko V., Yanushkevich S., A Genetic
Algorithm for Test Pattern
Generation for MVL Circuits, Proc. of the Int. Conference on Modelling
and Simulation, Spain, pp. 151-156 |
| (1998) |
Shmerko V, Perkowski M., Rogers W., Dueck G.,
Yanushkevich S., Bio-Technologies
in Computing: The Promises and the Reality, Proc. of the Int. Conf. on
Computational Intelligence and Multimedia Applications, Australia,
pp.396-409 PDF FILE |
| (1998) |
Dueck G., Holowinski G., Malecki K., Shmerko V.,
Yanushkevich S., Development
of Zakrevskij's Minimization Strategy towards Arithmetical Polynomial
Domain,
Proc. of the 3rd Int. Workshop on Boolean Problems, Germany, pp.
101-108 PDF FILE |
| (1998) |
Dueck G., C.Moraga, Shmerko V., Yanushkevich S.,
East - West Conferences
as Scientific and Industrial Collaboration Strategies, Proc. of the
Int.
Workshop on European Scientific & Industrial Collaboration on
Promoting
Advanced Technologies in Manufacturing - WESIC'98, Spain, pp.
427-432 PDF FILE |
| (1998) |
Cheushev V., Shmerko V., Simovici D.,
Yanushkevich S., Functional Entropy
and Decision Trees, Proc. of the IEEE 28th Int. Symp. on
Multiple-Valued
Logic, Japan, pp.357-362 PDF
FILE |
| (1997) |
Yanushkevich S., Levashenko V., Moraga C., Fault
Models for Multiple-Valued
Combinational Circuits, Proc. of the Int. Conf. on Applications of
Computer
System, Szczecin, Poland, pp.309-314 |
| (1997) |
Simovici D., Shmerko V., Cheushev V.,
Yanushkevich S., Information
Estimation of Logic Functions, Proc. Int. Conf. on Applications of
Computer
System, Szczecin, Poland, pp.287-300 PDF
FILE |
| (1997) |
Shmerko V., Yanushkevich S., Levashenko V., Test
Pattern Generation
for Combinational MVL Networks based on Generalized D-algorithm, Proc.
27th IEEE Int. Symp. on Multiple-Valued Logic, Canada, pp.
139-144 PostScript
FILE |
| (1997) |
Soldek J., Shmerko V., Phillips P., Kukharev G.,
Rogers W., Yanushkevich
S., Biometric Technologies, Proceeding of the Int. Conference The
Biometrics:
Fraud prevention, Enhanced Service, Las Vegas, Nevada, USA,
pp.270-286
download: PDF FILE |
| (1997) |
Phil Phillips, Yanushkevich S., Modern
Conception of Information Security,
Proceeding of the Int. Conf. on Applications of Computer System,
Szczecin,
Poland, pp.42-52 |
| (1997) |
Gilewski J., Phillips P., Yanushkevich S., Popel
D., Education Aspects:
Handwriting Recognition - Neural Networks - Fuzzy Logic, Proceeding of
IEE International Conf. on Pattern Recognition & Information
Processing,
Minsk, Belarus, pp.39-47 |
| (1996) |
Yanushkevich S., Analogues of Boolean
Differences and Differentials
in Arithmetical Logic, Proc. Workshop on Boolean Problems, Freiberg,
Germany,
pp.115-120
download: PDF FILE |
| (1996) |
Shmerko V., Yanushkevich S., Malecki K., A Class
of Logic Design Problems
Solved Based on Parallel Computations of "Butterfly" Configurations
Proc.
of the Int. Conf. on Parallel and Distributed Processing Techniques and
Applications, Sunnyvale, California, USA, pp. 1589-1592
download: PDF
FILE |
| (1996) |
Jaroszewicz S., Shmerko V., Yanushkevich S.,
Exact Irredundant Searching
for a Minimal Reed-Muller Expansion for an Incompletely Specified MVL
Function,
Proc. Int. Conf. on Advanced Computer Systems - ACS'96, Poland, pp.
65-74
download: PDF FILE |
| (1996) |
Shmerko V., Yanushkevich S., Levashenko V.,
Bondar I., Techniques of
Computing Logic Derivatives for MVL Functions. Proc. of the 26th IEEE
Int.
Symp. on Multiple-Valued Logic, Spain, pp.267-272
download: PDF FILE |
| (1996) |
Kalganova T., Kochergov E., Zaitseva E.,
Yanushkevich S., A Genetic
Approach to Optimise Polynomial Forms of Incompletely Specified MVL
Functions.
Proc. of the AISB96 Workshop on Evolutionary Computing, Brighton, UK,
pp.89-102 PDF FILE |
| (1995) |
Yanushkevich S., Kaczmarek A., Antonenko V.,
Zaitseva E., Synthesis
of Arithmetical Forms of Boolean Functions on Neural Networks. Proc. of
the XII Int. Conf. on Systems Science, Wroclaw, Poland, vol.1,
pp.121-125 |
| (1995) |
Yanushkevich S., Arithmetical Canonical
Expansions of Boolean and MVL
Functions as Generalized Reed-Muller Series, Proc. of the IFIP 10.5
Int.
Workshop on Applications of the Reed-Muller Expansions in Circuit
Design,
Japan, pp.300-307 PDF
FILE |
| (1995) |
Yanushkevich S. 2D Boolean Differential
Transforms as Mathematical
Models of two-Dimensional Bar Codes. Proc. IAPR Int. Conf. on Pattern
Recognition
& Image Analysis, Minsk, Belarus, vol.1, pp.183-188 |
| (1995) |
Soldek J., Yanushkevich S., Genetic Algorithms
in Logic Design. Proc
of the Int. Conference on Computer-Aided Design of Discrete Devices,
Minsk,
Belarus, vol.1, pp.17-26 |
| (1995) |
Antonenko V., Guvakov I., Shmerko V., Kaczmarek
A., Yanushkevich S.,
Linear Arithmetical Forms of k-valued Functions. Proc. of the European
Conf. on Circuit Theory and Design, Turkey, pp.955-958 PDF
FILE |
| (1994) |
Yanushkevich S., Spectral and Differential
Methods to Synthesize Polynomial
Forms of MVL-Functions on Systolic Arrays. Proc. of the of the 5th Int.
Workshop on Spectral Techniques, Beijing, China, pp.78-93 |
| (1994) |
Yanushkevich S., Matrix Algorithms of Synthesis
of Polynomial Forms
for MVL-Functions. Proc. of the Int. Conf. on Parallel Processing and
Applied
Mathematics, Poland, pp.113-122 |
| (1993)* |
Yanushkevich S., Synthesis of Diagnostical Tests
for Video-processor
on Multivalued Elements by Logic Differential Calculus Methods. Proc.
of
the IEE Conf. on Pattern Recognition and Image Analysis, Minsk,
Belarus,
pp.25-29 |
| (1993)* |
Yanushkevich S., Algorithms for Convolution of
Polynomial Forms of
Boolean Functions and their Realization on Systolic Arrays. Proc. of
the
IEE Conf. on Pattern Recognition and Image Analysis, Minsk, Belarus,
pp.38-42 |
| (1993) |
Shmerko V., Yanushkevich S., Kochergov E.,
Systolic Arrays for Binary
Image Processing by Using Boolean Differential Operators. SPIE Proc. of
the Int. Conf. on High Definition Video, vol.1976, Germany,
pp.324-335 PostScript
FILE |
| (1993) |
Shmerko V., Yanushkevich S., Fault Detection in
Multivalued Logic Networks
by New Type of Derivatives of Multivalued Functions. Proc. of the
European
Conf. on Circuit Theory and Design, Switzerland,
pp.643-646 PostScript
FILE |
| (1990)* |
Kuzmitsky V., Shmerko V., Yanushkevich S.,
Binary Image Processing
Algorithms on Homogeneous Computing Environment. In book.: Using
Computers
for Signal Processing, Technical Univ., Riga, Latvia, pp.5-14 |
| (1989)* |
Kuzmitsky V., Shmerko V., Yanushkevich S.,
Architectural Principles
of Logic Processing of 2D Binary Arrays on Magnetic-Optical
Transparants.
Proc of the Conf. on Mathematical Methods of Pattern Recognition, Riga,
Latvia, pp.28-32 |
4. Proceedings of Workshops (non- Refereed Papers)
| (2001) |
S. Yanushkevich, V. Shmerko, On the 10th
Anniversary of ULSI Workshop:
History, Analysis, Researchers, Extended Abstracts of the 10th Int.
Workshop
on Post-Binary Ultra-Large Scale Integration Systems, Warsaw, Poland,
2001 PDF FILE |
| (2002) |
S. Yanushkevich, V. Shmerko, V. Malyugin, P.
Dziurzanski, Linearity
of Word-Level Circuit Models: New Understanding, 11th Int. Workshop on
Logic and Synthesis, New Orleans, USA |
| (2001) |
Yanushkevich S., Dziurzanski P., Information
Theory Method for Flexible
Network Synthesis, Extend Abstracts of the 10th Int. Workshop on Post
Binary
Ultra-Scale Intergration System - ULSI'01 PowerPoint
FILE |
| (1999) |
Simovici D. Yanushkevich S., Information Theory
Approach in Logic Design:
Results, Trends and Non-solved Problems, Extended Abstracts of the 8th
Int. Workshop on Post-Binary Ultra-Large Scale Integration Systems,
Germany,
pp.26-29 |
| (1999) |
Popel D., Cheushev V., Shmerko V., Yanushkevich
S., Information Theoretical
Approach for EXOR Minimization, Extended Abstracts of the 8th Int.
Workshop
on Post-Binary Ultra-Large Scale Integration Systems, Germany,
pp.32-33 PostScript FILE |
| (1999) |
Kolodziejczyk J., Opoka M., Yanushkevich S.,
Moraga C., Information
Measure in Evolutionary Circuit Design, Extended Abstracts of the 8th
Int.
Workshop on Post-Binary Ultra-Large Scale Integration Systems, Germany,
pp.30-31 |
| (1998) |
Levashenko V., Shakirin A., Yanushkevich S.,
Genetic Algorithm for
Testing MVL combinational Circuits, Extended Abstracts of the 7th Int.
Workshop on Post-Binary Ultra-Large Scale Integration Systems, Japan,
pp.
59-60 |
| (1998) |
Holowinski G., Levashenko V., Yanushkevich S.,
Moraga C., Some New
results on Experiments with Testing MVL Combinational Circuits due
Generalized
D-algorithm, Extended Abstracts of the 7th Int. Workshop on Post-Binary
Ultra-Large Scale Integration Systems, Japan, pp.
55-56 PDF FILE |
| (1997) |
Stankovic R., Stankovic M., Jankovic D., Shmerko
V., Yanushkevich S.,
Optimizing of Calculation of Logic Derivatives through Decision
Diagrams,
Extended Abstracts of the Int. Workshop on Post Binary Ultra-Large
Scale
Integration Systems, Antigonish, Nova Scotia, Canada, pp. 53-54 |
| (1997) |
Holowinski G., Shmerko V., Yanushkevich S.,
Parallel Algorithm for
Minimization Incompletely Specified MVL Functions in Reed-Muller
Domain,
Extended Abstracts of the Int. Workshop on Post Binary Ultra-Large
Scale
Integration Systems, Antigonish, Nova Scotia, Canada, pp. 51-52 |
| (1996) |
Shmerko V., Yanushkevich S., On a Using Decision
Diagrams to Compute
Logic and Arithmetic Polynomial Forms for Incompletely Specified MVL
Functions,
Extended Abstracts of the Int. Workshop on Post-Binary Ultra-Large
Scale
Integration Systems, Spain, pp.13-18 |
4. Certificates on Inventions
 |
| (1993)* |
No.1803908 (G06F 7/04). Module for
Computing Boolean Functions / Yanushkevich
S., Levashenko V., Morozova A., Shmerko V. |
| (1992)* |
No.1777132 (G06F 7/00,7/04). Device for
Computing Boolean Differentials
/ Kolodieva I., Paramonova N., Shmerko V., Yanushkevich S. |
| (1992)* |
No.1756879 (G06F 7/00). Device for
Recognition of Linearity of Boolean
Functions / Bondar I., Kuzmitsky V., Shmerko V., Yanushkevich S. |
| (1992)* |
No.1732785 (G06F 7/00). Device for Solving
Boolean Differential Equations
/ Shmerko V., Levashenko V., Yanushkevich S., Paramonov N. |
| (1992)* |
No.1730617 (G06F 7/04). Module for
Computing Logic Derivatives / Antonenko
V., Zaitseva E., Shmerko V., Yanushkevich S. |
| (1991)* |
No.1686460 (G06F 15/353) Device for
Computing Implicants/ Bondar I.,
Dubrova E., Shmerko V.,Yanushkevich S. |
| (1991)* |
No.1667050 (G06F 15/334). Module for Logic
Transforms of Boolean Functions
/ Shmerko V., Yanushkevich S., Morozova A., Kukharev G. |
| (1991)* |
No.1661791 (G06F 15/332). Device for
Solving Boolean Differential Equations
/ Shmerko V., Yanushkevich S., Levashenko V., Kukharev G. |
| (1990)* |
No.1566365 (G06F 15/334). Device for
Differentiation of Logic Functions
/ Shmerko V., Dashenkov V., Zaitseva E., Tupikov V.,Yanushkevich S. |
| (1990)* |
No.1541592 (G06F 15/334). Device for Logic
Differentiation and Integration
of Boolean Functions / Shmerko V., Yanushkevich S., Zaitseva E.,
Kukharev
G. |
|
| (1990)* |
No.1541591 (G06F 15/334) Device for Logic
Differentiation of Boolean
Functions / Shmerko V., Yanushkevich S., Zaitseva E., Kukharev G. |
| (1990)* |
No.1532946 (G06F 15/334). Device for
Transform of Boolean Functions
/ Shmerko V., Kuzmitsky D., Dashenkov V., Yanushkevich S. |
| (1989)* |
No.1522957 (G06F 15/334). Device for
Solving Logic Equations Systems
/ Shmerko V., Golovetskaya N., Dashenkov V., Yanushkevich S. |
| (1989)* |
No.1481793 (G06F 15/334). Device for
Computing Boolean Differences
/ Dashenkov V., Shmerko V., Kuzmitsky D., Tupikov V., Yanushkevich S. |
|
5. Technical and Research Reports
| (2000) |
Research Report, Flexibility in Logic Design: An
Approach Based on
Information Theory Methods, V. Cheshev, S. Yanushkevich, C. Moraga, V.
Shmerko, Forschungsbericht 741, University of Dortmund,
Germany Post
Script FILE |
| (2000) |
Research Report, Recognition of Symmetries in
Logic Functions. Visiting
program between Technical University of Szczecin (Poland) and
University
of New Brunswick (Canada). Grant by State Committee for Scientific
Research
(Poland) |
| (2000) |
Research Report, Information Measures of Logic
Functions. Visiting
program between Technical University of Szczecin (Poland) and State
University
of Informatics and Radioelectronics (Belarus). Grant by State Committee
for Scientific Research (Poland) |
| (2000)** |
Research Report, Joint research visit program
between Poland and Yugoslavia,
Grant of Polish State Committee for Scientific Research NKZ-KBN/5d/99,
Theme No. 5/99 Solving of logic design problems using novel
decomposition
and minimization algorithms", supervisors Prof. S.Yanushkevich, Prof.
R.
Stankovic, Technical Univ., Szczecin, Poland |
| (1999)** |
Research Report "Multiple-Valued Logic Design",
Grant of State Committee
for Scientific Research of Poland, Supervisor Dr S. Yanushkevich,
Technical
Univ., Szczecin, Poland |
| (1998-2000)** |
Research Report, Joint visit program between
Poland and Canada, Grant
of Polish State Committee for Scientific Research NKZ-KBN/5d/98, Theme
No. 5/98 "Solving of logic design problems using novel decomposition
and
minimization algorithms", supervisors Prof. V. Shmerko, Prof. G. Dueck,
Technical Univ., Szczecin, Poland |
| (1998-1999)** |
Research Report, Joint visit program between
Poland and Belarus, Grant
of Polish State Committee for Scientific Research NKZ-KBN/6d/98, Theme
No. 8/98,"Investigation of Reduced Methods of Optimization of Logic
Functions",
supervisors Dr. S.Yanushkevich, Dr. S. Pottosina, Technical Univ.,
Szczecin,
Poland |
| (1998) |
Research Report TR98-1: "Optimal polarity for
Reed-Muller and arithmetic
expansion of symmetric logic functions", Supervisor G. Dueck, Dept. of
Mathematics, Statistics and Computer Science, St. Francis Xavier
University,
Antigonish, Canada |
| (I-1998)* |
Research Report: "Methods of Information Theory
for Design of Digital
Networks and Telecommunication", Grant of Fund of Fundamental
Researches,
National Academy of Sciences, Task 3.4, Supervisor Dr S. Yanushkevich,
State Univ. of Informatics & Radioelectronics, Minsk, Belarus |
| (1998)* |
Research Report "Logic Differential Calculus
Theory", Grant of Fund
of Fundamental Researches, National Academy of Sciences, Task 3.2,
Supervisor
Dr S. Yanushkevich, State Univ. of Informatics & Radioelectronics,
Minsk, Belarus |
| (1997)** |
Research Report, Joint visit program between
Poland, Germany and Belarus,
Grant of Polish State Committee for Scientific Research Nr
NKZ-KBN/4/97,
theme No. 1/97 "Application of Logic Differential Calculus and Spectral
Methods in Optimization Problems of CAD Systems", supervisors Prof.
V.Shmerko,
Prof. C.Moraga, Dr. E.Zaitseva, Inst. of Computer Sci. &
Information
Systems, Technical Univ., Szczecin, Poland |
| (1997)** |
Research Report, Joint visit program between
Poland, UK and Belarus
, Grant of Polish State Committee for Scientific Research Z/16/2/97,
Theme
No. 2/97,"Developing the Methods of Optimisation of Incompletely
Specified
Multiple-Valued Logic Functions based on Evolutionary Algorithms",
Supervisors
Dr S. Yahushkevich, Dr J. Miller, Dr S. Pottosina, Inst. of Computer
Sci.
& Information Systems, Technical Univ., Szczecin, Poland |
| (1997)* |
Research Report 97-1045 "Training Specialists on
Computer Technology,
Nets, Internet and Intranet", Grant of Ministry of Education &
Sci.,
State Univ. of Informatics & Radioelectronics, supervisor Prof. V.
Shmerko, Belarus |
| (1996-1998)** |
Research Report, Joint visit program between
Poland and Belarus (Polish
State Committee for Scientific Researches): "Identification of
Signature
and Handwriting Based on Neural Networks Technologies and Genetic
Algorithms"
- Agreement no. KBN 3906/DZ/96, Theme No. 6/96, supervisors Prof.
V.Shmerko,
Dr S.Pottosina, Inst. of Computer Sci. & Information Systems,
Technical
Univ., Szczecin, Poland |
| (1996)** |
Research Report on Personal Grant of Polish
Committee for Scientific
Research No. 21-0119/17-99-00 (RKH\BW)) "Logic Differential Calculus in
Modern Logic Design of Multivalued Devices", Inst. of Computer Sci.
&
Information Systems, Technical Univ., Szczecin, Poland |
| (1995)** |
Research Report "Methods and Parallel Algorithms
of Logic Differential
Equations for Synthesis and Analysis of Discrete Devices",Grant
no.000-0602/17-00-00
(02\BW\94), Supervisor V.Shmerko, Technical Univ., Szczecin, Poland |
| (I-1995)* |
Research Report 93-3032 "Application of Logic
Differential Calculus
Theory", Grant no.199-41-086 of Informatization Fund, supervisor V.
Shmerko,
State Univ. of Informatics & Radioelectronics, Minsk, Belarus |
| (I-1995)* |
Research Report 93-3028 " Methods and Algorithms
of Arithmetical Logic",
Grant of Informatization Fund, supervisor V. Shmerko, State Univ. of
Informatics
& Radioelectronics, Minsk, Belarus |
| (I-1994)* |
Research Report 94-8028 " Instrumental Tools for
Image Processing",
Grant of Fund of Informatization, supervisor V. Shmerko, State Univ. of
Informatics & Radioelectronics, Minsk, Belarus |
| (I-1994)* |
Research Report 94-3048 "Instrumental Tools of
Applied Theory of Logic
Differential Calculus", Grant No.199-43-363 of Informatization Fund,
supervisor
V.Shmerko, State Univ. of Informatics & Radioelectronics, Minsk,
Belarus |
| (I-1994)* |
Research Report 93-3052 "Applied Theory of Logic
Differential Calculus",
Grant no.199-41-086 of Informatization Fund, supervisor S.
Yanushkevich,
State Univ. of Informatics & Radioelectronics, Minsk, Belarus |
| (I-1992)* |
Research Report 92-3097 "Parallel Algorithms and
Hardware for Logic
Data Processing", Grant of Fund of Informatization, supervisor V.
Shmerko,
State Univ. of Informatics & Radioelectronics, Minsk, Belarus |
<*> - in Russian,
<**> - In Polish
|